1. Field of the Invention
The invention relates to circuits and methods for priority encoding. More specifically, the invention relates to a priority encoder implemented exclusively with static circuits devoid of ROM or other memory circuit components.
2. Discussion of Related Art
A wide variety of electronic systems utilize bus structures in which multiple devices communicate via a shared bus. The bus may comprise a plurality of signal paths for exchanging discrete signals and/or may comprise serial communication pass in which multiple signals are transmitted sequentially over the serial signal paths. In such shared bus structures, the multiple devices generally arbitrate for temporary exclusive control of the shared bus structure. Thus, one device (often referred to as a master device) may initiate communications with one or more other devices coupled to the shared bus structure.
Typically in such a system, a device referred to as an arbiter or arbitrator may determine which of multiple master devices may be granted requested temporary control of the shared bus structure. A common approach for designing such an arbiter includes a priority encoder that receives multiple request or hitlines signal paths often from a content addressable memory (“CAM”) or other signal sources. Each signal, regardless of the source, may represent one of multiple master devices sharing the common bus structure and requesting temporary exclusive access. The priority encoder then determines from the multiple request signal paths which device is to be granted the requested temporary exclusive control. Such an arbiter in a shared bus structure is but one exemplary application of such a priority encoder circuit. Those of ordinary skill in the art will recognize a wide variety of other applications and systems that may beneficially apply a priority encoder circuit.
A common application using such priority encoder circuits utilizes a content addressable memory (CAM). A CAM is used to compare a multiple bit input word signal to all multiple bit words stored in the CAM. The output of the CAM indicates the location of the matching word or words—i.e., one “hitline” per matching word of the CAM. Typically, the output of the CAM device is applied to a prioritizer that selects the highest priority hitline that is presently active in the output bits of the CAM. The highest priority bit is then applied to a ROM the output of which indicates the encoded index value of the identified highest priority active hitline. The prioritizer and ROM thereby translate the CAM output into a corresponding encoded address for the highest priority hitline—e.g., the highest priority device presently requesting temporary exclusive access to the shared bus.
As semiconductors fabrication techniques further reduce the size of circuit structures and spacing of interconnecting signal paths within integrated circuits, known priority encoders using ROM devices have become problematic. For example many present day semiconductor fabrication technologies produce component sizes and signal path traces approaching 90 nm or less. With such high density circuits, circuit designs have to account more specifically for channel leakage associated with the decreased size of circuits within an integrated circuit die. ROM devices in particular suffer from this channel leakage problem and hence present increased problems for present-day integrated circuit designs with ROM based priority encoders.
It is evident from the above discussion that a need exists for improved circuit structures and methods for priority encoding that avoids utilization of ROM structures susceptible to channel leakage and other problems as integrated circuit density continues to increase.